The invention relates generally to a DRAM memories and, more specifically, to a fault tolerant design for such memories.
In the past large digital memories have been implemented using large arrays of one bit DRAM (Dynamic Random Access Memories), i.e., DRAM made up of a very large number of single bit cells. More recently, DRAM made up of 4-bit cells has become popular and the prices of such devices have dropped sufficiently to make their use in systems requiring RAM or cache storage more practical. However, the 4-bit DRAM has characteristics that are different from the single bit DRAM. For example, one cannot simply write directly to a single bit location in one of the 4-bit cells within the DRAM chip but rather must write to all four locations in the cell. These differences have produced some issues regarding how to utilize the 4-bit DRAM in existing system designs.